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512kx36/x32 & 1mx18 synchronous sram - 1 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a document title 512kx36/x32 & 1mx18-bit synchronous pipelined burst sram the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to c hange the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. revision history rev. no. 0.0 0.1 0.2 remark preliminary preliminary preliminary history 1. initial draft 1. add jtag scan order 1. add x32 org and industrial temperature . 2. add 165fbga package draft date feb. 23. 2001 may. 10. 2001 aug. 30. 2001
512kx36/x32 & 1mx18 synchronous sram - 2 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a 16mb sb/spb synchronous sram ordering information org. part number mode vdd speed sb ; access time(ns) spb ; cycle time(mhz) pkg temp 1mx18 k7b161825a-q(h/f)c(i)65/75/85 sb 3.3 6.5/7.5/8.5ns q : 100tqfp h : 119bga f : 165fbga c (commercial temperature range) i (industrial temperature range) k7a161800a-q(h/f)c(i)16/14 spb(2e1d) 3.3 167/138mhz k7a161809a-q(h/f)c(i)25/22/20 spb(2e1d) 3.3 250/225/200mhz k7a161801a-qc(i)16/14 spb(2e2d) 3.3 167/138mhz k7a161808a-qc(i)25/22/20 spb(2e2d) 3.3 250/225/200mhz 512kx32 k7b163225a-qc(i)65/75/85 sb 3.3 6.5/7.5/8.5ns k7a163200a-qc(i)16/14 spb(2e1d) 3.3 167/138mhz k7a163209a-qc(i)25/22/20 spb(2e1d) 3.3 250/225/200mhz k7a163201a-qc(i)16/14 spb(2e2d) 3.3 167/138mhz k7a163208a-qc(i)25/22/20 spb(2e2d) 3.3 250/225/200mhz 512kx36 k7b163625a-q(h/f)c(i)65/75/85 sb 3.3 6.5/7.5/8.5ns k7a163600a-q(h/f)c(i)16/14 spb(2e1d) 3.3 167/138mhz k7a163609a-q(h/f)c(i)25/22/20 spb(2e1d) 3.3 250/225/200mhz k7a163601a-qc(i)16/14 spb(2e2d) 3.3 167/138mhz k7a163608a-qc(i)25/22/20 spb(2e2d) 3.3 250/225/200mhz
512kx36/x32 & 1mx18 synchronous sram - 3 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a 512kx36/x32 & 1mx18-bit synchronous pipelined burst sram the k7a163609a, k7a163209a and k7a161809a are 18,874,368-bit synchronous static random access mem- ory designed for high performance second level cache of pentium and power pc based system. it is organized as 512k(1m) words of 36(32/18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache ram applications; gw , bw , lbo , zz. write cycles are internally self-timed and synchronous. full bus-width write is done by gw , and each byte write is performed by the combination of we x and bw when gw is high. and with cs 1 high, adsp is blocked to control sig- nals. burst cycle can be initiated with either the address status processor( adsp ) or address status cache control- ler( adsc ) inputs. subsequent burst addresses are gener- ated internally in the system s burst sequence and are controlled by the burst address advance( adv ) input. lbo pin is dc operated and determines burst sequence(linear or interleaved). zz pin controls power down state and reduces stand-by current regardless of clk. the k7a163609a, k7a163209a and k7a161809a are fab- ricated using samsung s high performance cmos tech- nology and is available in a 100pin tqfp, 119bga and 165fbga package. multiple power and ground pins are utilized to minimize ground bounce. general description features logic block diagram ? synchronous operation. ? 2 stage pipelined operation with 4 burst. ? on-chip address counter. ? self-timed write cycle. ? on-chip address and control registers. ? v dd = 3.3v +0.165v/-0.165v power supply. ? i/o supply voltage 3.3v +0.165v/-0.165v for 3.3v i/o or 2.5v+0.4v/-0.125v for 2.5v i/o. ? 5v tolerant inputs except i/o pins. ? byte writable function. ? global write enable controls a full bus-width write. ? power down state via zz signal. ? lbo pin allows a choice of either a interleaved burst or a linear burst. ? three chip enables for simple depth expansion with no data con- tention only for tqfp ; 2cycle enable, 1cycle disable. ? asynchronous output enable control. ? adsp , adsc , adv burst control pins. ? ttl-level three-state output. ? 100-tqfp-1420a / 119bga(7x17 ball grid array package) ? 165fbga(11x15 ball aray) with body size of 13mmx15mm. ? operating in commeical and industrial temperature range. clk lbo adv adsc adsp cs 1 cs 2 cs 2 gw bw we x oe zz dqa 0 ~ dqd 7 or dqa0 ~ dqb7 burst control logic burst 512kx36/32 , 1mx18 address control output data-in address counter memory array register register buffer logic c o n t r o l r e g i s t e r c o n t r o l r e g i s t e r a 0 ~a 1 a 0 ~a 1 or a 2 ~a 19 or a 0 ~a 19 register dqpa ~ dqpd a 0 ~a 18 a 2 ~a 18 (x=a,b,c,d or a,b) dqpa,dqpb fast access times parameter symbol -25 -22 -20 unit cycle time tcyc 4.0 4.4 5.0 ns clock access time tcd 2.6 2.8 3.1 ns output enable access time toe 2.6 2.8 3.1 ns
512kx36/x32 & 1mx18 synchronous sram - 4 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a pin configuration (top view) pin name symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 18 adv adsp adsc clk cs 1 cs 2 cs 2 we x(x=a,b,c,d) oe gw bw zz lbo address inputs burst address advance address status processor address status controller clock chip select chip select chip select byte write inputs output enable global write enable byte write enable power down input burst mode control 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50,81,82,99,100 83 84 85 89 98 97 92 93,94,95,96 86 88 87 64 31 v dd v ss n.c. dqa 0 ~a 7 dqb 0 ~b 7 dqc 0 ~c 7 dqd 0 ~d 7 dqpa~p d or nc v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs output power supply (3.3v or 2.5v) output ground 15,41,65,91 17,40,67,90 14,16,38,39,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) nc/dqpc dqc 0 dqc 1 v ddq v ssq dqc 2 dqc 3 dqc 4 dqc 5 v ssq v ddq dqc 6 dqc 7 n.c. v dd n.c. v ss dqd 0 dqd 1 v ddq v ssq dqd 2 dqd 3 dqd 4 dqd 5 v ssq v ddq dqd 6 dqd 7 nc/dqpd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqpb/nc dqb 7 dqb 6 v ddq v ssq dqb 5 dqb 4 dqb 3 dqb 2 v ssq v ddq dqb 1 dqb 0 v ss n.c. v dd zz dqa 7 dqa 6 v ddq v ssq dqa 5 dqa 4 dqa 3 dqa 2 v ssq v ddq dqa 1 dqa 0 dqpa/nc 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 a 6 a 7 c s 1 c s 2 w e d w e c w e b w e a c s 2 v d d v s s c l k g w b w o e a d s c a d s p a d v a 8 8 1 a 9 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 a 1 7 a 1 8 v d d v s s n . c . n . c . a 0 a 1 a 2 a 3 a 4 a 5 3 1 l b o a 1 6 k7a163609a(512kx36) k7a163209a(512kx32)
512kx36/x32 & 1mx18 synchronous sram - 5 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a pin configuration (top view) pin name note : 1. a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 19 adv adsp adsc clk cs 1 cs 2 cs 2 we x(x=a,b) oe gw bw zz lbo address inputs burst address advance address status processor address status controller clock chip select chip select chip select byte write inputs output enable global write enable byte write enable power down input burst mode control 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 v dd v ss n.c. dqa 0 ~ a 7 dqb 0 ~ b 7 dqpa, pb v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs output power supply (3.3v or 2.5v) output ground 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29 30,38,39,51,52,53,56,57 66,75,78,79,95,96 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) n.c. n.c. n.c. v ddq v ssq n.c. n.c. dqb 0 dqb 1 v ssq v ddq dqb 2 dqb 3 n.c. v dd n.c. v ss dqb 4 dqb 5 v ddq v ssq dqb 6 dqb 7 dqpb n.c. v ssq v ddq n.c. n.c. n.c. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 n.c. n.c. v ddq v ssq n.c. dqpa dqa 7 dqa 6 v ssq v ddq dqa 5 dqa 4 v ss n.c. v dd zz dqa 3 dqa 2 v ddq v ssq dqa 1 dqa 0 n.c. n.c. v ssq v ddq n.c. n.c. n.c. 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 a 6 a 7 c s 1 c s 2 n . c . n . c . w e b w e a c s 2 v d d v s s c l k g w b w o e a d s c a d s p a d v a 8 8 1 a 9 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 8 a 1 9 v d d v s s n . c . n . c . a 0 a 1 a 2 a 3 a 4 a 5 3 1 l b o a 1 6 a 1 7 a 10 k7a161809a(1mx18)
512kx36/x32 & 1mx18 synchronous sram - 6 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a 119bga package pin configurations (top view) k7a163609a(512kx36) note : * a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 a v ddq a a adsp a a v ddq b nc a a adsc a a nc c nc a a v dd a a nc d dqc dqpc v ss nc v ss dqpb dqb e dqc dqc v ss cs 1 v ss dqb dqb f v ddq dqc v ss oe v ss dqb v ddq g dqc dqc we c adv we b dqb dqb h dqc dqc v ss gw v ss dqb dqb j v ddq v dd nc v dd nc v dd v ddq k dqd dqd v ss clk v ss dqa dqa l dqd dqd we d nc we a dqa dqa m v ddq dqd v ss bw v ss dqa v ddq n dqd dqd v ss a 1 * v ss dqa dqa p dqd dqpd v ss a 0 * v ss dqpa dqa r nc a lbo v dd nc a nc t nc nc a a a nc zz u v ddq tms tdi tck tdo nc v ddq pin name symbol pin name symbol pin name a a 0 , a 1 adv adsp adsc clk cs 1 we x (x=a,b,c,d) oe gw bw zz lbo tck tms tdi tdo address inputs burst count address burst address advance address status processor address status controller clock chip select byte write inputs output enable global write enable byte write enable power down input burst mode control jtag test clock jtag test mode select jtag test data input jtag test data output v dd v ss n.c. dqa dqb dqc dqd dqpa~pd v ddq power supply(+3.3v) ground no connect data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outpus output power supply (2.5v or 3.3v)
512kx36/x32 & 1mx18 synchronous sram - 7 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a 119bga package pin configurations (top view) k7a161809a(1mx18) note : * a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 a v ddq a a adsp a a v ddq b nc a a adsc a a nc c nc a a v dd a a nc d dqb nc v ss nc v ss dqpa nc e nc dqb v ss cs 1 v ss nc dqa f v ddq nc v ss oe v ss dqa v ddq g nc dqb we b adv v ss nc dqa h dqb nc v ss gw v ss dqa nc j v ddq v dd nc v dd nc v dd v ddq k nc dqb v ss clk v ss nc dqa l dqb nc v ss nc we a dqa nc m v ddq dqb v ss bw v ss nc v ddq n dqb nc v ss a 1 * v ss dqa nc p nc dqpb v ss a 0 * v ss nc dqa r nc a lbo v dd nc a nc t nc a a nc a a zz u v ddq tms tdi tck tdo nc v ddq pin name symbol pin name symbol pin name a a 0 ,a 1 adv adsp adsc clk cs 1 we x (x=a,b) oe gw bw zz lbo tck tms tdi tdo address inputs burst count address burst address advance address status processor address status controller clock chip select byte write inputs output enable global write enable byte write enable power down input burst mode control jtag test clock jtag test mode select jtag test data input jtag test data output v dd v ss n.c. dqa dqb dqpa~pb v ddq power supply(+3.3v) ground no connect data inputs/outputs data inputs/outputs data inputs/outpus output power supply (2.5v or 3.3v)
512kx36/x32 & 1mx18 synchronous sram - 8 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a 165-pin fgba package configurations (top view) k7a163609a(512kx36) note : * a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 8 9 10 11 a nc a cs 1 we c we b cs 2 bw adsc adv a nc b nc a cs2 we d we a clk gw oe adsp a nc c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb h nc v ss nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa n dqpd nc v ddq v ss nc a v ss v ss v ddq nc dqpa p nc nc a a tdi a 1 * tdo a a a a r lbo nc a a tms a 0 * tck a a a a pin name symbol pin name symbol pin name a a 0 , a 1 adv adsp adsc clk cs 1 we x (x=a,b,c,d) oe gw bw zz lbo tck tms tdi tdo address inputs burst count address burst address advance address status processor address status controller clock chip select byte write inputs output enable global write enable byte write enable power down input burst mode control jtag test clock jtag test mode select jtag test data input jtag test data output v dd v ss n.c. dqa dqb dqc dqd dqpa~pd v ddq power supply(+3.3v) ground no connect data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outpus output power supply (2.5v or 3.3v)
512kx36/x32 & 1mx18 synchronous sram - 9 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a pin name symbol pin name symbol pin name a a 0 ,a 1 adv adsp adsc clk cs 1 we x (x=a,b) oe gw bw zz lbo tck tms tdi tdo address inputs burst count address burst address advance address status processor address status controller clock chip select byte write inputs output enable global write enable byte write enable power down input burst mode control jtag test clock jtag test mode select jtag test data input jtag test data output v dd v ss n.c. dqa dqb dqpa~pb v ddq power supply(+3.3v) ground no connect data inputs/outputs data inputs/outputs data inputs/outpus output power supply (2.5v or 3.3v) 165-pin fgba package configurations (top view) k7a161809a(1mx18) note : * a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 8 9 10 11 a nc a cs 1 we b nc cs 2 bw adsc adv a a b nc a cs2 nc we a clk gw oe adsp a nc c nc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpa d nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa e nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa f nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa g nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa h nc v ss nc v dd v ss v ss v ss v dd nc nc zz j dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc k dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc l dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc m dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc n dqpb nc v ddq v ss nc a v ss v ss v ddq nc nc p nc nc a a tdi a 1 * tdo a a a a r lbo nc a a tms a 0 * tck a a a a
512kx36/x32 & 1mx18 synchronous sram - 10 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a function description the k7a163609a, k7a163209a and k7a161809a are synchronous sram designed to support the burst address accessing sequence of the power pc based microprocessor. all inputs (with the exception of oe , lbo and zz) are sampled on rising clock edges. the start and duration of the burst access is controlled by adsc , adsp and adv and chip select pins. the accesses are enabled with the chip select signals and output enabled signals. wait states are inserted into the access with adv . when zz is pulled high, the sram will enter a power down state. at this time, internal state of the sram is preserved. when zz returns to low, the sram normally operates after 2cycles of wake up time. zz pin is pulled down internally. read cycles are initiated with adsp (regardless of we x and adsc )using the new external address clocked into the on-chip address register whenever adsp is sampled low, the chip selects are sampled active, and the output buffer is enabled with oe . in read oper- ation the data of cell array accessed by the current address, registered in the data-out registers by the positive edge of clk, are car- ried to the data-out buffer by the next positive edge of clk. the data, registered in the data-out buffer, are projected to the output pins. adv is ignored on the clock edge that samples adsp asserted, but is sampled on the subsequent clock edges. the address increases internally for the next access of the burst when we x are sampled high and adv is sampled low. and adsp is blocked to control signals by disabling cs 1 . all byte write is done by gw (regaedless of bw and we x.), and each byte write is performed by the combination of bw and we x when gw is high. write cycles are performed by disabling the output buffers with oe and asserting we x. we x are ignored on the clock edge that sam- ples adsp low, but are sampled on the subsequent clock edges. the output buffers are disabled when we x are sampled low(regaedless of oe ). data is clocked into the data input register when we x sampled low. the address increases internally to the next address of burst, if both we x and adv are sampled low. individual byte write cycles are performed by any one or more byte write enable signals( we a, we b, we c or we d) sampled low. the we a control dqa 0 ~ dqa 7 and dqpa, we b controls dqb 0 ~ dqb 7 and dqpb, we c controls dqc 0 ~ dqc 7 and dqpc, and we d control dqd 0 ~ dqd 7 and dqpd. read or write cycle may also be initi- ated with adsc , instead of adsp . the differences between cycles initiated with adsc and adsp as are follows; adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . we x are sampled on the same clock edge that sampled adsc low(and adsp high). addresses are generated for the burst access as shown below, the starting point of the burst sequence is provided by the externa l address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the st ate of the lbo pin. when this pin is low, linear burst sequence is selected. when this pin is high, interleaved burst sequence is selected. burst sequence table (interleaved burst) lbo pin high case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 bq table (linear burst) note : 1. lbo pin must be tied to high or low, and floating state must not be allowed . lbo pin low case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 asynchronous truth table operation zz oe i/o status sleep mode h x high-z read l l dq l h high-z write l x din, high-z deselected l x high-z notes 1. x means "don t care". 2. zz pin is pulled down internally 3. for write cycles that following read cycles, the output buffers must be disabled with oe , otherwise data bus contention will occur. 4. sleep mode means power down state of which stand-by current does not depend on cycle time. 5. deselected means power down state of which stand-by current depends on cycle time.
512kx36/x32 & 1mx18 synchronous sram - 11 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a synchronous truth table notes : 1. x means "don t care". 2. the rising edge of clock is symbolized by - . 3. write = l means write operation in write truth table. write = h means read operation in write truth table. 4. operation finally depends on status of asynchronous input pins(zz and oe ). cs 1 cs 2 cs 2 adsp adsc adv write clk address accessed operation h x x x l x x - n/a not selected l l x l x x x - n/a not selected l x h l x x x - n/a not selected l l x x l x x - n/a not selected l x h x l x x - n/a not selected l h l l x x x - external address begin burst read cycle l h l h l x l - external address begin burst write cycle l h l h l x h - external address begin burst read cycle x x x h h l h - next address continue burst read cycle h x x x h l h - next address continue burst read cycle x x x h h l l - next address continue burst write cycle h x x x h l l - next address continue burst write cycle x x x h h h h - current address suspend burst read cycle h x x x h h h - current address suspend burst read cycle x x x h h h l - current address suspend burst write cycle h x x x h h l - current address suspend burst write cycle truth tables write truth table (x36 / x32) notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( - ). gw bw we a we b we c we d operation h h x x x x read h l h h h h read h l l h h h write byte a h l h l h h write byte b h l h h l l write byte c and d h l l l l l write all bytes l x x x x x write all bytes write truth table (x18) notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( - ). gw bw we a we b operation h h x x read h l h h read h l l h write byte a h l h l write byte b h l l l write all bytes l x x x write all bytes
512kx36/x32 & 1mx18 synchronous sram - 12 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a capacitance* (t a =25 c, f=1mhz) *note : sampled not 100% tested. parameter symbol test condition min max unit input capacitance c in v in =0v - 5 pf output capacitance c out v out =0v - 7 pf operating conditions at 3.3v i/o (0 c t a 70 c) parameter symbol min typ. max unit supply voltage v dd 3.135 3.3 3.465 v v ddq 3.135 3.3 3.465 v ground v ss 0 0 0 v operating conditions at 2.5v i/o (0 c t a 70 c) parameter symbol min typ. max unit supply voltage v dd 3.135 3.3 3.465 v v ddq 2.375 2.5 2.9 v ground v ss 0 0 0 v absolute maximum ratings* *note : stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0.3 to 4.6 v voltage on v ddq supply relative to v ss v ddq v dd v voltage on input pin relative to v ss v in -0.3 to v dd +0.3 v voltage on i/o pin relative to v ss v io -0.3 to v ddq +0.3 v power dissipation p d 1.6 w storage temperature t stg -65 to 150 c operating temperature commercial t opr 0 to 70 c industrial t opr -40 to 85 c storage temperature range under bias t bias -10 to 85 c
512kx36/x32 & 1mx18 synchronous sram - 13 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a v ss v ih v ss- 1.0v 20% t cyc (min) test conditions parameter value input pulse level(for 3.3v i/o) 0 to 3.0v input pulse level(for 2.5v i/o) 0 to 2.5v input rise and fall time(measured at 20% to 80% for 3.3v i/o) 1.0v/ns input rise and fall time(measured at 20% to 80% for 2.5v i/o) 1.0v/ns input and output timing reference levels for 3.3v i/o 1.5v input and output timing reference levels for 2.5v i/o v ddq /2 output load see fig. 1 (v dd =3.3v+0.165v/-0.165v , v ddq =3.3v+0.165/-0.165v or v dd =3.3v+0.165v/-0.165v , v ddq =2.5v+0.4v/-0.125v, t a =0to70 c) dc electrical characteristics (v dd =3.3v+0.165v/-0.165v , t a =0 c to +70 c) notes : 1. reference ac operating conditions and characteristics for input and timing. 2. data states are all zero. 3. in case of i/o pins, the max. v ih =v ddq +0.3v. parameter symbol test conditions min max unit notes input leakage current(except zz) i il v dd = max ; v in =v ss to v dd -2 +2 m a output leakage current i ol output disabled, v out =v ss to v ddq -2 +2 m a operating current i cc device selected, i out =0ma, zz v il , cycle time 3 t cyc min -25 - 440 ma 1,2 -22 - 400 -20 - 370 standby current i sb device deselected, i out =0ma, zz v il , f=max, all inputs 0.2v or 3 v dd -0.2v -25 - 120 ma -22 - 110 -20 - 100 i sb1 device deselected, i out =0ma, zz 0.2v, f = 0, all inputs=fixed (v dd -0.2v or 0.2v) - 70 ma i sb2 device deselected, i out =0ma, zz 3 v dd -0.2v, f=max, all inputs v il or 3 v ih - 60 ma output low voltage(3.3v i/o) v ol i ol =8.0ma - 0.4 v output high voltage(3.3v i/o) v oh i oh =-4.0ma 2.4 - v output low voltage(2.5v i/o) v ol i ol =1.0ma - 0.4 v output high voltage(2.5v i/o) v oh i oh =-1.0ma 2.0 - v input low voltage(3.3v i/o) v il -0.3* 0.8 v input high voltage(3.3v i/o) v ih 2.0 v dd +0.3** v 3 input low voltage(2.5v i/o) v il -0.3* 0.7 v input high voltage(2.5v i/o) v ih 1.7 v dd +0.3** v 3
512kx36/x32 & 1mx18 synchronous sram - 14 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a output load(b), (for t lzc , t lzoe , t hzoe & t hzc ) dout 353 w / 1538 w 5pf* +3.3v for 3.3v i/o 319 w / 1667 w fig. 1 * including scope and jig capacitance output load(a) dout zo=50 w rl=50 w vl=1.5v for 3.3v i/o v ddq /2 for 2.5v i/o /+2.5v for 2.5v i/o 30pf* ac timing characteristics (v dd =3.3v+0.165v/-0.165v , t a =0 c to +70 c) notes : 1. all address inputs must meet the specified setup and hold times for all rising clock edges whenever adsc and/or adsp is sampled low and cs is sampled low. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected . 2. both chip selects must be active whenever adsc or adsp is sampled low in order for the this device to remain enabled. 3. adsc or adsp must not be asserted for at least 2 clock after leaving zz state. parameter symbol -25 -22 -20 unit min max min max min max cycle time t cyc 4.0 - 4.4 - 5.0 - ns clock access time t cd - 2.6 - 2.8 - 3.1 ns output enable to data valid t oe - 2.6 - 2.8 - 3.1 ns clock high to output low-z t lzc 0 - 0 - 0 - ns output hold from clock high t oh 0.8 - 1.0 - 1.0 - ns output enable low to output low-z t lzoe 0 - 0 - 0 - ns output enable high to output high-z t hzoe - 2.6 - 2.8 - 3.0 ns clock high to output high-z t hzc 0.8 2.6 1.0 2.8 1.0 3.0 ns clock high pulse width t ch 1.7 - 1.8 - 2.0 - ns clock low pulse width t cl 1.7 - 1.8 - 2.0 - ns address setup to clock high t as 1.2 - 1.4 - 1.4 - ns address status setup to clock high t ss 1.2 - 1.4 - 1.4 - ns data setup to clock high t ds 1.2 - 1.4 - 1.4 - ns write setup to clock high ( gw , bw , we x ) t ws 1.2 - 1.4 - 1.4 - ns address advance setup to clock high t advs 1.2 - 1.4 - 1.4 - ns chip select setup to clock high t css 1.2 - 1.4 - 1.4 - ns address hold from clock high t ah 0.3 - 0.4 - 0.4 - ns address status hold from clock high t sh 0.3 - 0.4 - 0.4 - ns data hold from clock high t dh 0.3 - 0.4 - 0.4 - ns write hold from clock high ( gw , bw , we x ) t wh 0.3 - 0.4 - 0.4 - ns address advance hold from clock high t advh 0.3 - 0.4 - 0.4 - ns chip select hold from clock high t csh 0.3 - 0.4 - 0.4 - ns zz high to power down t pds 2 - 2 - 2 - cycle zz low to power up t pus 2 - 2 - 2 - cycle
512kx36/x32 & 1mx18 synchronous sram - 15 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction dose not places dqs in hi-z. ir2 ir1 ir0 instruction tdo output notes 0 0 0 sample-z boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 bypass bypass register 3 1 0 0 sample boundary scan register 4 1 0 1 bypass bypass register 3 1 1 0 bypass bypass register 3 1 1 1 bypass bypass register 3 ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible teat access port(tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction reg- ister, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap controll er without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected. tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo pi pi tdi tms tck test logic reset run test idle 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1
512kx36/x32 & 1mx18 synchronous sram - 16 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit(0) 512kx36 0000 00111 00100 xxxxxx 00001001110 1 1mx18 0000 01000 00011 xxxxxx 00001001110 1 scan register definition part instruction register bypass register id register boundary scan 512kx36 3 bits 1 bits 32 bits 75 bits 1mx18 3 bits 1 bits 32 bits 75 bits 119bga boundary scan exit order(x36) 1 2t nc clk 4k 39 2 1r nc adv 4g 40 3 4t a adsc 4b 41 4 4h gw adsp 4a 42 5 5r nc bw 4m 43 6 5t a we c 3g 44 7 5l we a a 3b 45 8 7r nc a 3a 46 9 6r a a 2b 47 10 7t zz cs 1 4e 48 11 6p dqpa a 3c 49 12 7n dqa a 2c 50 13 6m dqa a 2a 51 14 7l dqa dqpc 2d 52 15 6k dqa dqc 1e 53 16 7p dqa dqc 2f 54 17 6n dqa dqc 1g 55 18 6l dqa dqc 2h 56 19 7k dqa dqc 1d 57 20 5j nc dqc 2e 58 21 6h dqb dqc 2g 59 22 7g dqb dqc 1h 60 23 6f dqb dqd 2k 61 24 7e dqb dqd 1l 62 25 7d dqb dqd 2m 63 26 7h dqb dqd 1n 64 27 6g dqb dqd 1p 65 28 6e dqb dqd 1k 66 29 6d dqpb dqd 2l 67 30 7b nc dqd 2n 68 31 6c a dqpd 2p 69 32 5c a we d 3l 70 33 6a a lbo 3r 71 34 5b a a 2r 72 35 5a a a 3t 73 36 4f oe a1 4n 74 37 5g we b a0 4p 75 38 6b a 119bga boundary scan exit order(x18 ) 1 2t a clk 4k 39 2 1r nc adv 4g 40 3 6t a adsc 4b 41 4 4h gw adsp 4a 42 5 5r nc bw 4m 43 6 5t a we b 3g 44 7 5l we a a 3b 45 8 7r nc a 3a 46 9 6r a a 2b 47 10 7t zz cs 1 4e 48 11 6p nc a 3c 49 12 7n nc a 2c 50 13 6m nc a 2a 51 14 7l nc nc 2d 52 15 6k nc nc 1e 53 16 7p dqa nc 2f 54 17 6n dqa nc 1g 55 18 6l dqa nc 2h 56 19 7k dqa dqb 1d 57 20 5j nc dqb 2e 58 21 6h dqa dqb 2g 59 22 7g dqa dqb 1h 60 23 6f dqa dqb 2k 61 24 7e dqa dqb 1l 62 25 6d dqpa dqb 2m 63 26 7h nc dqb 1n 64 27 6g nc dqpb 2p 65 28 6e nc nc 1k 66 29 7d nc nc 2l 67 30 7b nc nc 2n 68 31 6c a nc 1p 69 32 5c a nc 3l 70 33 6a a lbo 3r 71 34 5b a a 2r 72 35 5a a a 3t 73 36 4f oe a1 4n 74 37 5g nc a0 4p 75 38 6b a note, nc ; don t care
512kx36/x32 & 1mx18 synchronous sram - 17 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a 165fbga boundary scan exit order(x36) 1 1r lbo clk 6b 39 2 6n a nc 11b 40 3 11p a nc 1a 41 4 8p a cs 2 6a 42 5 8r a we a 5b 43 6 9r a we b 5a 44 7 9p a we c 4a 45 8 10p a we d 4b 46 9 10r a cs2 3b 47 10 11r a cs 1 3a 48 11 11h zz a 2a 49 12 11n dqa a 2b 50 13 11m dqa nc 1b 51 14 11l dqa dqc 1c 52 15 11k dqa dqc 1d 53 16 11j dqa dqc 1e 54 17 10m dqa dqc 1f 55 18 10l dqa dqc 1g 56 19 10k dqa dqc 2d 57 20 10j dqa dqc 2e 58 21 11g dqb dqc 2f 59 22 11f dqb dqc 2g 60 23 11e dqb dqd 1j 61 24 11d dqb dqd 1k 62 25 10g dqb dqd 1l 63 26 10f dqb dqd 1m 64 27 10e dqb dqd 2j 65 28 10d dqb dqd 2k 66 29 11c dqb dqd 2l 67 30 11a nc dqd 2m 68 31 10a a dqd 1n 69 32 10b a a 3p 70 33 9a adv a 3r 71 34 9b adsp a 4r 72 35 8a adsc a 4p 73 36 8b oe a1 6p 74 37 7a bw a0 6r 75 38 7b gw 165fbga boundary scan exit order(x18 ) 1 1r lbo clk 6b 39 2 6n a nc 11b 40 3 11p a nc 1a 41 4 8p a cs 2 6a 42 5 8r a we a 5b 43 6 9r a nc 5a 44 7 9p a we b 4a 45 8 10p a nc 4b 46 9 10r a cs2 3b 47 10 11r a cs 1 3a 48 11 11h zz a 2a 49 12 11n nc a 2b 50 13 11m nc nc 1b 51 14 11l nc nc 1c 52 15 11k nc nc 1d 53 16 11j nc nc 1e 54 17 10m dqa nc 1f 55 18 10l dqa nc 1g 56 19 10k dqa dqb 2d 57 20 10j dqa dqb 2e 58 21 11g dqa dqb 2f 59 22 11f dqa dqb 2g 60 23 11e dqa dqb 1j 61 24 11d dqa dqb 1k 62 25 11c dqa dqb 1l 63 26 10f nc dqb 1m 64 27 10e nc dqb 1n 65 28 10d nc nc 2k 66 29 10g nc nc 2l 67 30 11a a nc 2m 68 31 10a a nc 2j 69 32 10b a a 3p 70 33 9a adv a 3r 71 34 9b adsp a 4r 72 35 8a adsc a 4p 73 36 8b oe a1 6p 74 37 7a bw a0 6r 75 38 7b gw note, nc ; don t care
512kx36/x32 & 1mx18 synchronous sram - 18 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a jtag timing diagram jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5 - ns tms input hold time t chmx 5 - ns tdi input setup time t dvch 5 - ns tdi input hold time t chdx 5 - ns sram input setup time t svch 5 - ns sram input hold time t chsx 5 - ns clock low to output valid t clqv 0 10 ns tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx jtag dc operating conditions note : the input level of sram pin is to follow the sram dc specification . 1. in case of i/o pins, the max. v ih =v ddq +0.3v. parameter symbol min typ max unit note power supply voltage v dd 3.135 3.3 3.465 v input high level ( 3.3v i/o / 2.5v i/o ) v ih 2.0 / 1.7 - v dd +0.3 v 1 input low level ( 3.3v i/o / 2.5v i/o ) v il -0.3 - 0.8 / 0.7 v output high voltage( 3.3v i/o / 2.5v i/o ) v oh 2.4 / 2.0 - - v output low voltage( 3.3v i/o / 2.5v i/o ) v ol - - 0.4 / 0.4 v jtag ac test conditions parameter symbol min unit note input high/low level( 3.3v i/o , 2.5v i/o ) v ih /v il 3.0/0 , 2.5/0 v input rise/fall time( 3.3v i/o , 2.5v i/o ) tr/tf 1.0/1.0 , 1.0/1.0 ns input and output timing reference level v ddq /2 v
512kx36/x32 & 1mx18 synchronous sram - 19 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a c l o c k a d s p a d s c a d d r e s s w r i t e c s a d v o e d a t a o u t t i m i n g w a v e f o r m o f r e a d c y c l e n o t e s : w r i t e = l m e a n s g w = l , o r g w = h , b w = l , w e x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l t c h t c l t s s t s h t s s t s h t a s t a h a 1 a 2 a 3 b u r s t c o n t i n u e d w i t h n e w b a s e a d d r e s s t w s t w h t c s s t c s h t a d v s t a d v h t o e t h z o e t l z o e t c d t o h ( a d v i n s e r t s w a i t s t a t e ) t h z c q 3 - 4 q 3 - 3 q 3 - 2 q 3 - 1 q 2 - 4 q 2 - 3 q 2 - 2 q 2 - 1 q 1 - 1 d o n t c a r e u n d e f i n e d t c y c
512kx36/x32 & 1mx18 synchronous sram - 20 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a t i m i n g w a v e f o r m o f w r t e c y c l e c l o c k a d s p a d s c a d d r e s s w r i t e c s a d v d a t a i n t c h t c l t s s t s h t a s t a h a 1 a 2 a 3 ( a d s c e x t e n d e d b u r s t ) d 2 - 1 d 1 - 1 t c s s t c s h ( a d v s u s p e n d s b u r s t ) d 2 - 2 d 2 - 3 d 2 - 4 d 3 - 1 d 3 - 2 d 3 - 3 d 2 - 2 d 3 - 4 q 0 - 3 q 0 - 4 o e d a t a o u t t s s t s h t w s t w h t a d v s t a d v h t d s t d h t h z o e d o n t c a r e u n d e f i n e d t c y c
512kx36/x32 & 1mx18 synchronous sram - 21 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a t i m i n g w a v e f o r m o f c o m b i n a t i o n r e a d / w r t e c y c l e ( a d s p c o n t r o l l e d , a d s c = h i g h ) c l o c k a d s p a d d r e s s w r i t e c s a d v o e d a t a o u t t c h t c l t d s t d h q 3 - 2 d a t a i n t o h a 1 a 2 a 3 d 2 - 1 q 3 - 1 q 3 - 3 t s s t s h t a s t a h t w s t w h t a d v s t a d v h t l z o e t h z o e t c d t h z c q 3 - 4 t l z c q 1 - 1 d o n t c a r e u n d e f i n e d t c y c
512kx36/x32 & 1mx18 synchronous sram - 22 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a t i m i n g w a v e f o r m o f s i n g l e r e a d / w r i t e c y c l e ( a d s c c o n t r o l l e d , a d s p = h i g h ) c l o c k a d s c a d d r e s s w r i t e c s a d v o e d a t a i n t c h t c l t h z o e d 6 - 1 d a t a o u t t w s t w h t l z o e t o h t o e d 5 - 1 d 7 - 1 t w s t w h t l z o e t d h t d s a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 q 3 - 1 q 1 - 1 q 2 - 1 q 4 - 1 q 8 - 1 t c s s t c s h t s s t s h q 9 - 1 d o n t c a r e u n d e f i n e d t c y c
512kx36/x32 & 1mx18 synchronous sram - 23 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a t i m i n g w a v e f o r m o f p o w e r d o w n c y c l e c l o c k a d s p a d d r e s s w r i t e c s a d v d a t a i n t c h t c l d 2 - 2 o e t h z o e d 2 - 1 a 1 t s s t s h d a t a o u t t p u s a d s c z z t a s t a h t c s s t c s h s l e e p s t a t e n o r m a l o p e r a t i o n m o d e z z r e c o v e r y c y c l e a 2 t w s t w h t l z o e q 1 - 1 t o e t h z c t p d s z z s e t u p c y c l e d o n t c a r e u n d e f i n e d t c y c
512kx36/x32 & 1mx18 synchronous sram - 24 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a application information the samsung 512kx36 synchronous pipelined burst sram has two additional chip selects for simple depth expansion. depth expansion this permits easy secondary cache upgrades from 512k depth to 1m depth without extra logic. data address clk ads cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 512kx36 spb sram (bank 0) cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 512kx36 spb sram (bank 1) clk address cache controller a [0:19] a [19] a [0:18] a [19] a [0:18] i/o [0:71] microprocessor clock adsp address data out bank 0 is selected by cs 2 , and bank 1 deselected by cs 2 q1-1 q1-2 q1-4 q1-3 oe data out t ss t sh a1 a2 write cs 1 a n+1 adv (bank 0) (bank 1) q2-2 q2-4 q2-3 t as t ah t ws t wh t advs t advh t oe t lzoe t hzc bank 0 is deselected by cs 2 , and bank 1 selected by cs 2 t css t csh t cd t lzc [0:n] q2-1 interleave read timing (refer to non-interleave write timing for interleave write timing) don t care undefined ( adsp controlled , adsc =high) *notes : n = 14 32k depth , 15 64k depth 16 128k depth , 17 256k depth 18 512k depth , 19 1m depth
512kx36/x32 & 1mx18 synchronous sram - 25 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a application information depth expansion data address clk ads microprocessor cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 1mx18 spb sram (bank 0) cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 1mx18 spb sram (bank 1) clk address cache controller a [0:20] a [20] a [0:19] a [20] a [0:19] i/o [0:71] clock adsp address data out bank 0 is selected by cs 2 , and bank 1 deselected by cs 2 q1-1 q1-2 q1-4 q1-3 oe data out t ss tsh don t care a1 a2 write cs 1 a n+1 adv (bank 0) (bank 1) q2-2 q2-4 q2-3 t as t ah t ws t wh t advs t advh t oe t lzoe thzc bank 0 is deselected by cs 2 , and bank 1 selected by cs 2 t css tcsh t cd t lzc [0:n] undefined q2-1 interleave read timing (refer to non-interleave write timing for interleave write timing) ( adsp controlled , adsc =high) the samsung 1mx18 synchronous pipelined burst sram has two additional chip selects for simple depth expansion. this permits easy secondary cache upgrades from 1m depth to 2m depth without extra logic. *notes : n = 14 32k depth , 15 64k depth 16 128k depth , 17 256k depth 18 512k depth , 19 1m depth 20 2m depth
512kx36/x32 & 1mx18 synchronous sram - 26 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a package dimensions 0.10 max 0~8 22.00 0.30 20.00 0.20 16.00 0.30 14.00 0.20 1.40 0.10 1.60 max 0.05 min (0.58) 0.50 0.10 #1 (0.83) 0.50 0.10 100-tqfp-1420a 0.65 0.30 0.10 0.10 max + 0.10 - 0.05 0.127 units ; millimeters/inches
512kx36/x32 & 1mx18 synchronous sram - 27 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a 119 bga package dimensions 0.750 0.15 1.27 1.27 12.50 0.10 0.60 0.10 0.60 0.10 1.50ref c1.00 c0.70 14.00 0.10 22.00 0.10 20.50 0.10 note : 1. all dimensions are in millimeters. 2. solder ball to pcb offset : 0.10 max. 3. pcb to cavity offset : 0.10 max. indicator of ball(1a) location
512kx36/x32 & 1mx18 synchronous sram - 28 - rev 0.2 aug 2001 k7a161809a k7a163209a preliminary k7a163609a 165 fbga package dimensions c side view 13mm x 15mm body, 1.0mm bump pitch, 11x15 ball array f a ? h g b bottom view top view a b d e e symbol value units note symbol value units note a 15 0.1 mm e 1.0 mm b 13 0.1 mm f 14.0 mm c 1.3 0.1 mm g 10.0 mm d 0.35 0.05 mm h 0.45 0.05 mm

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